Article ID: 000077945 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why is the QDRII SRAM UniPHY based controller IP not generating QVLD signal for the interface?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

QVLD signal is not generated because it is not used by the QDRII SRAM UniPHY based controller IP to determine if the data coming back is valid or not.

QDRII SRAM UniPHY based IP uses calibration process to determing the exact read latency i.e. how long does it take for the valid data to come back from the QDRII SRAM device after a read command is given by the IP.

Related Products

This article applies to 8 products

Stratix® V GS FPGA
Stratix® V GT FPGA
Stratix® V GX FPGA
Stratix® V E FPGA
Stratix® IV E FPGA
Stratix® IV GT FPGA
Stratix® IV GX FPGA
Stratix® III FPGAs

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