Article ID: 000077956 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why does ALTLVDS_TX megafunction not support my outclock divide factor?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

There is a problem with the ALTLVDS_TX megafunction in the Quartus®  II software version 9.0.

The ALTLVDS_TX MegaWizard™ Plug-In incorrectly disallows the use of the outclock divide factor (B) settings on tx_outclock port that give an output clock frequency between 717 and 800 MHz for Stratix®  III or Stratix IV C2 speed grade devices.

To fix this problem, follow these steps:

  1. Open a command prompt
  2. Navigate to the directory that contains the wizard-generated wrapper file
  3. Type the following command, with the relevant B factor and filename:

    qmegawiz -silent OUTCLOCK_DIVIDE_BY=<B factor> <altlvds_tx design file.v|vhd|tdf>

Alternatively, manually edit the wizard-generated wrapper file to change the outclock_divide_by parameter to the desired B factor.

This problem is fixed in the Quartus II software version 9.1.

Related Products

This article applies to 2 products

Stratix® III FPGAs
Stratix® IV FPGAs