Article ID: 000078191 Content Type: Troubleshooting Last Reviewed: 05/15/2013

Why does scanclk disappear when enabling both Dynamic Phase Shifting and Dynamic Reconfiguration options in the Altera_PLL megafunction?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description The scanclk is not available when you have enabled both Dynamic Phase Shifting and Dynamic Reconfiguration options in the Altera_PLL megafunction. You can synchronize the Dynamic Phase Shift control signals to the mgmt_clk signal which is available as an input port on the Altera_PLL_RECONFIG block.

Related Products

This article applies to 15 products

Stratix® V GS FPGA
Arria® V GZ FPGA
Cyclone® V E FPGA
Cyclone® V GX FPGA
Arria® V GT FPGA
Stratix® V GT FPGA
Stratix® V E FPGA
Stratix® V GX FPGA
Arria® V GX FPGA
Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Arria® V ST SoC FPGA
Arria® V SX SoC FPGA
Cyclone® V SE SoC FPGA
Cyclone® V ST SoC FPGA