Article ID: 000078341 Content Type: Troubleshooting Last Reviewed: 01/21/2015

Why does 64-bit Addressing in the Avalon-Memory Mapped (Avalon MM) Hard IP for PCI Express not function properly for Cyclone V & Arria V?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description Due to a problem in the RTL, the 64-bit addressing in the Hard IP for PCI Express® for Cyclone® V and Arria® V requires the following code changes.
    Resolution

    The file altpcie_cv_hip_avmm_hwtcl.v line 214 should be changed from

    parameter CB_P2A_AVALON_ADDR_B0 = 32\'h01000000,

    to

    parameter CB_P2A_AVALON_ADDR_B0 = 32\'h00000000,

    The file is found in the following directory:

    <your Quartus install directory>\ip\altera\altera_pcie\altera_pcie_cv_hip_avmm\altpcie_cv_hip_avmm_hwtcl.v

    You must regenerate the IP after modifying the above file.

    After regeneration, you must modify the file altpciexpav_stif_txavl_cntrl.v  in your current project directory, find line 213

    assign pcie_space_64 = bypass_trans? 1\'b0 : PCIeAddrSpace_i[0];

    and replace it with:

    assign pcie_space_64 = bypass_trans? 1\'b1 : PCIeAddrSpace_i[0];

    This is scheduled to be fixed in a future release of the Quartus II software.

    Related Products

    This article applies to 1 products

    Cyclone® V GX FPGA