Article ID: 000078357 Content Type: Troubleshooting Last Reviewed: 03/02/2015

Can the Hard IP for PCI Express initiate PCI Express loopback?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Only Root Port configurations of the Altera®  Hard IP for PCI Express® support loopback mastering.

Endpoint configurations support loopback slave entry.

Resolution

To initiate PCI Express loopback mastering when configured as a Root Port, set the hip_ctrl_test_in to 32\'hAA.

For normal operation set hip_ctrl_test_in to 32\'hA8.

Related Products

This article applies to 1 products

Stratix® V GX FPGA