Article ID: 000078625 Content Type: Troubleshooting Last Reviewed: 03/25/2013

Is it possible to perform boundary scan testing over the Hard Processor System (HPS) JTAG pins?

Environment

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Description

No, it is not possible to perform boundary scan testing over the HPS JTAG pins. However tbe HPS I/O pins do support boundary scan testing through the JTAG pins of the FPGA. The BSDL files generated via the Quartus® II software for Cyclone® V SoC devices will include HPS I/O pins that support boundary scan.

Note: For Cyclone V SoC FPGAs you must power up both the HPS and FPGA to perform a boundary scan test (BST).

Related Products

This article applies to 3 products

Cyclone® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Cyclone® V SE SoC FPGA