Due to a problem in the Quartus® II software version 12.1 and later, you might see this error in Arria® V devices when using the ALTLVDS_TX Intel® FPGA IP in external PLL mode.
Error: SERDES DPA Block node 'lvds_tx:lvds_tx_inst0|altlvds_tx:ALTLVDS_TX_component|lvds_tx_lvds_tx:auto_generated|arriav_serdes_dpa1' is not properly connected on the 'TXFCLK' port. It must be connected to one of the valid ports listed below.Info: Can be connected to LVDSCLK port of arriav_pll_lvds_output WYSIWYGInfo: Can be connected to OUTCLK port of generic_pll WYSIWYG
To work around this problem, an LVDS buffer needs to be inserted between the external PLL and the ALTLVDS instance on the tx_inclock and the tx_enable ports.
Refer to a related solution under the Related Article section to learn how you can add an intermediate LVDS buffer between the external PLL and ALTLVDS Intel FPGA IP.