Article ID: 000079316 Content Type: Troubleshooting Last Reviewed: 02/10/2016

Why are the fPLL C counters not updated correctly when dynamically reconfiguring an Altera_PLL using the Altera_PLL_Reconfig IP?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

When using Altera_PLL_Reconfig, the translation logic from C logical counter to C physical counter may map incorrectly in the Quartus® II software versions 13.1 and earlier, causing the IP to reconfigure the wrong physical counter.

Resolution

Disable the ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP assignment in your project. Current versions of the Quartus II software must have this assignment disabled in order for C output counters to be updated dynamically.  The IP is scheduled to  be enhanced in a future version of the Quartus II software to allow you to use the ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP assignment and dynamic reconfiguration of the C output counters.

You can refer to AN 661: Implementing Fractional PLL Reconfiguration with ALTERA_PLL and ALTERA_PLL_RECONFIG Megafunctions (PDF).

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This article applies to 14 products

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