Article ID: 000079434 Content Type: Troubleshooting Last Reviewed: 12/10/2013

Why does the local_cal_success go high but local_init_done stay low during RTL simulation for the hard memory controller?

Environment

  • Intel® Quartus® Prime Standard Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    When running an RTL simulation for the UniPHY-based hard memory controller in Arria® V or Cyclone® V device, you may find local_cal_success go high but local_init_done stay low. The local_init_done signal is driven by the hard memory controller based on the internally synchronized version of the afi_cal_success input. The local_init_done and local_cal_success signals should have the same behavior. However, they may have different behaviors if the the clock input or reset input for the multi port front-end (MPFE) is not correctly connected.

    Resolution

    Make sure the MPFE clock and reset ports are properly connected.

    Related Products

    This article applies to 5 products

    Arria® V GT FPGA
    Cyclone® V FPGAs and SoC FPGAs
    Arria® V GX FPGA
    Arria® V ST SoC FPGA
    Arria® V SX SoC FPGA