Critical Issue
Description
This problem affects DDR2 and DDR3, LPDDR2, QDR II, and RLDRAM II products.
An internal error can occur in designs targeting Arria V or Cyclone V devices and using a hard memory controller, when the MPFE, MMR, and SC clock inputs for the hard memory controller are not driven by a PLL or by a clock buffer.
Resolution
The workaround for this issue is to ensure that you drive the MPFE, MMR, and SC clock inputs through a PLL.
This issue will be fixed in a future version.
