This problem affects DDR2, DDR3, and LPDDR2 products.
External memory interfaces targeting Cyclone V devices may exhibit timing failure on paths from the following nodes to the FPGA core:
The workaround for this issue is as follows:
- Restrict the placement of core nodes to meet timing requirements.
- Compile the IP using multiple seeds and additional synthesis and fitter optimizations enabled.
This issue will be fixed in a future version.