Article ID: 000079554 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Does Stratix V QDRII/ SDRAM Controller at full rate have timing closure issue?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description Yes, you might experience out of box timing violations with Stratix® V QDRII/ at full rate. This issue will be fixed in a future Quartus® II software and IP version.
    Resolution

    To workaround this issue, in the SDC file locate these lines:

                    if {} {

                                    set_clock_uncertainty -to [get_clocks _*] -add -hold 0.200

                                    set_clock_uncertainty -to [get_clocks _*] -add -hold 0.100

                                    set_clock_uncertainty -to [get_clocks _*] -add -hold 0.160

                    }

    and change them to

                    if {} {

                                    set_clock_uncertainty -to [get_clocks _*] -add -hold 0.400

                                    set_clock_uncertainty -to [get_clocks _*] -add -hold 0.150

                                    set_clock_uncertainty -to [get_clocks _*] -add -hold 0.225

     

                                    set_clock_uncertainty -to [get_clocks _*] -add -setup 0.200

                    }

    Related Products

    This article applies to 4 products

    Stratix® V GX FPGA
    Stratix® V E FPGA
    Stratix® V GT FPGA
    Stratix® V GS FPGA