Article ID: 000079609 Content Type: Troubleshooting Last Reviewed: 09/23/2011

Stratix V Clock Networks Incorrect

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    The Quartus II software does not correctly model the timing performance of clock networks in Stratix V ES devices when both edges of the clock signal are used. Affects Stratix V engineering sample devices.

    Resolution

    Refer to the Stratix V datasheet for applicable clock frequency limits in this case.

    Related Products

    This article applies to 1 products

    Stratix® V FPGAs