Article ID: 000080153 Content Type: Product Information & Documentation Last Reviewed: 03/09/2015

How to close timing on competing hold and setup violations in Arria 10?


  • Quartus® II Subscription Edition
    Description In Arria® 10 devices, the Quartus® II fitter automatically packs registers into an Adaptive Logic Module (ALM) in order to optimize area. If a hold-critical register gets packed in the same ALM as its driving LUT, the router will add wire in front of the LUT to avoid hold time violations. This can negatively affect a setup critical path going through the same LUT and it becomes difficult to fix both setup and hold time violations around this structure.

    A new Quartus Settings File (.QSF) assignment is available that prevents the automatic packing of the register and its driving LUT into the same ALM. This allows the router to add the necessary hold fixing wire directly in front of the register and does not negatively affect the setup critical path through the LUT itself.

    In order to prevent register/LUT packing, use the following assignment:

    set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to <inst_name>

    This assignment is available in the Quartus II software version 14.0 Arria 10 edition and later. Future releases of the Quartus II software are scheduled to handle this automatically.

    Related Products

    This article applies to 3 products

    Intel® Arria® 10 GT FPGA
    Intel® Arria® 10 GX FPGA
    Intel® Arria® 10 SX SoC FPGA



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