Article ID: 000080678 Content Type: Error Messages Last Reviewed: 02/19/2020

Error (18694): The reference clock on PLL "qsys_top_0|a10_tse_mac_pcs|a10_tse_mac_pcs|i_lvdsio_rx_0|core|arch_inst|internal_pll.pll_inst|altera_lvds_core20_iopll", which feeds an Altera LVDS SERDES IP instance, is not driven by a dedicated reference clock

Environment

  • Intel® Quartus® Prime Pro Edition
  • Intel® Quartus® Prime Standard Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition version 18.1 software onwards and Intel® Quartus® Prime Standard Edition version 19.1 software onwards, the user will encounter the below Intel® Quartus® project design compilation error when using the Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference Design from AN647.

    The error is due to LVDS reference clock is being manually promoted to global clock through the QSF assignment shown below in the reference design.

     set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to ref_clk

     

    Error (18694): The reference clock on PLL "qsys_top_0|a10_tse_mac_pcs|a10_tse_mac_pcs|i_lvdsio_rx_0|core|arch_inst|internal_pll.pll_inst|altera_lvds_core20_iopll", which feeds an Altera LVDS SERDES IP instance, is not driven by a dedicated reference clock pin from the same bank. Use a dedicated reference clock pin to guarantee meeting the LVDS SERDES IP max data rate specification.

     

    Resolution

    To work around this problem, manually disable the promotion of LVDS refclk via the QSF assignment shown below 

    set_instance_assignment -name GLOBAL_SIGNAL OFF -to ref_clk

     

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