Why is the generated clock is not correct when there are multiple Intel® P-Tile Avalon-ST for PCI Express instances?

Due to a problem in the Intel® Quartus® Prime Pro Edition software version 20.3, PCIe clocks may not be generated correctly when there are multiple Intel P-Tile Avalon-ST for PCI Express instances with different configurations. This problem occurs in designs targeting Intel® Agilex® P-Tile devices. The IP generated SDC file includes wildcards for matching the clock path, this results in only the first PCIe IP's SDC file being read correctly.

To work around the problem, use the attached SDC file to replace the one generated in <IP instance>/intel_pcie_ptile_ast_310/synth/intel_ptile_pcie.sdc. 

intel_ptile_pcie.sdc

The problem is fixed in the Intel® Quartus® Prime Pro Edition software version 20.4.