Article ID: 000080968 Content Type: Troubleshooting Last Reviewed: 09/11/2012

What happens to p_clk, core_clk_out and Avalon interface width when the PCIe core down-trains?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The PCI Express® core always operates as specified in the original configuration. The core_clk_out and Avalon® Interface width remain unchanged.

For example, assumming the Hard IP PCIe core is configured as Gen2x8, with pclk=500MHz, core_clk_out=250MHz, and Avalon width=128. If it is downtrained to Gen1x1, it will operate in Gen1 settings with pclk=250MHz, core_clk_out=250MHz, and Avalon width=128.

The above description applies to both Hard IP and Soft IP.

Related Products

This article applies to 5 products

Stratix® IV GX FPGA
Stratix® IV GT FPGA
Arria® II GX FPGA
Arria® II GZ FPGA
Cyclone® IV GX FPGA

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