Due to a problem in the Quartus® II software version 14.0, you might see the Fitter error above when compiling the Seriallite III Intel® FPGA IP for Stratix® V devices.
You can extract the following parameters from the earlier v13.1.4 Seriallite III Intel FPGA IP top level RTL file and then transfer them to the 14.0 Seriallite III Intel FPGA IP version.
reference_clock_frequency => "xxx.x MHz",
pll_ref_freq => "xxx.x MHz",
data_rate => "xxxxx.x Mbps"
Alternatively, you can use the 13.1.4 Seriallite III Intel FPGA IP version of the RTL and compile this in Quartus II software v14.0.
This problem has been fixed in the Quartus II software 14.0.1 and onwards.