Article ID: 000081479 Content Type: Troubleshooting Last Reviewed: 06/19/2013

Why do I get the error message similar to below when compiling a PCI Express design in Quartus II software for Cyclone V devices?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    This error message is due to incorrect nPERST pin placement in the PCIe® IP core.  For example, you will get this error message if you use pin nPERSTL0 with the bottom left HIP in Cyclone® V devices.  See the full error message below. 

    Error (175001): Could not place Hard IP
        Info (175028): The Hard IP name: <top level instantiation>|altpcie_cv_hip_ast_hwtcl:dut|altpcie_av_hip_ast_hwtcl:altpcie_av_hip_ast_hwtcl|
    altpcie_av_hip_128bit_atom:altpcie_av_hip_128bit_atom|arriav_hd_altpe2_hip_top
        Error (10104): Unable to find a path between I/O pad and PINPERST port of PCI Express Hard IP.
            Error (10151): "HIP_X1_Y15_N0" is not a legal location for "I/O pad" connected to PINPERSTN of PCI Express Hard IP.
            Info (10371): 2 potential locations for I/O pad: PIN_W24, PIN_Y23.
            Info (175029): 1 location affected
                Info (175029): HIP_X1_Y15_N0

    Resolution

    The correct mapping for nPERSTL0 and nPERSTL1 in Cyclone® V device is:

    Bottom PCIe Hard IP --> nPERSTL1
    Top PCIe Hard IP  --> nPERSTL0
    This mapping is opposite for Stratix® V and Arria® V devices where bottom PCIe Hard IP is associated with nPERSTL0, top PCIe Hard IP is associated with nPERSTL1.

    Related Products

    This article applies to 2 products

    Cyclone® V GT FPGA
    Cyclone® V GX FPGA

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