Article ID: 000082653 Content Type: Error Messages Last Reviewed: 03/16/2023

Error (175020): Illegal constraint of fractional PLL to the region (x-coordinate, y- coordinate) to (x-coordinate, y-coordinate): no valid locations in region

Environment

  • Quartus® II Subscription Edition
  • PLL
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    This error can occur in Stratix® V, Arria® V, and Cyclone® V devices when the PLL Intel® FPGA IP is sourced by a global or regional  network where that network is driven by a dedicated clock input pin.  The connection of a dedicated clock pin to a phase-locked loop (PLL) over a global / regional network is legal, however, the Quartus® II software will not allow this connection without an explicit promotion of the clock to the global or regional resource through a clock control block.

    Resolution

    Insert an ALTCLKCTRL Intel® FPGA IP in the clock path between the dedicated clock input pin and the PLL Intel FPGA IP.  Note, using a global primitive or global signal assignment for the clock signal is not sufficient, the ALTCLKCTRL Intel® FPGA IP must be instantiated in your design.

    This is not necessary when the clock input pin has dedicated access to the PLL Intel FPGA IP. 

    Related Products

    This article applies to 15 products

    Cyclone® V GT FPGA
    Stratix® V GX FPGA
    Cyclone® V GX FPGA
    Stratix® V GT FPGA
    Stratix® V GS FPGA
    Arria® V GZ FPGA
    Arria® V SX SoC FPGA
    Cyclone® V ST SoC FPGA
    Arria® V ST SoC FPGA
    Arria® V GX FPGA
    Arria® V GT FPGA
    Cyclone® V E FPGA
    Stratix® V E FPGA
    Cyclone® V SX SoC FPGA
    Cyclone® V SE SoC FPGA