Due to a problem in the Quartus® II software versions 14.1 and earlier you may see this warning when connecting the input of a bidirectional buffer to a constant zero when targeting the Arria® 10 device family.
The problem occurs due to a synthesis problem in which the OE and IN ports for the bidirectional buffer are switched.
The synthesis problem impacts all other device families however the warning is currently only issued for the Arria 10 device family
To work around this problem, use the "keep" attribute to preserve the constant wire as shown in the code below:
For VHDL:
signal const_zero_sig : std_logic;
attribute keep: boolean;
attribute keep of const_zero_sig: signal is true;
begin
const_zero_sig <= \'0\';
TRI_PIN <= const_zero_sig when ENABLE=\'1\' else \'Z\';
For Verilog HDL:
wire const_zero_sig /* synthesis keep */;
assign const_zero_sig = 1\'b0;
assign TRI_PIN = enable? const_zero_sig : \'bz;
This problem is scheduled to be fixed in a future release of the Quartus II software.
