Article ID: 000084096 Content Type: Troubleshooting Last Reviewed: 03/16/2023

Why are there timing violations within my PLL Reconfig Intel® FPGA IP?

Environment

  • Avalon ALTPLL
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The maximum frequency for the mgmt_clk and scanclk reconfiguration clock inputs for PLL reconfiguration are specified in the respective device datasheets for Stratix® V, Arria® V, and Cyclone® V devices with the symbol tDYCONFIGCLK.

     

    Resolution

    The PLL Reconfig Intel® FPGA IP might require a lower clock frequency to achieve timing closure.  You should use the Timing Analyzer to ensure that your choice of clock frequency for mgmt_clk and/or scanclk will meet the timing requirements of your chosen device.

    Related Products

    This article applies to 15 products

    Cyclone® V SE SoC FPGA
    Cyclone® V SX SoC FPGA
    Cyclone® V GT FPGA
    Stratix® V GX FPGA
    Stratix® V GT FPGA
    Cyclone® V GX FPGA
    Stratix® V GS FPGA
    Arria® V GZ FPGA
    Arria® V SX SoC FPGA
    Cyclone® V ST SoC FPGA
    Arria® V ST SoC FPGA
    Arria® V GX FPGA
    Arria® V GT FPGA
    Cyclone® V E FPGA
    Stratix® V E FPGA