When using zero delay compensation (ZDB) in a Stratix® III or Stratix IV device PLL, you must instantiate a bidirectional pin and connect that to the fbmimicbidir port of the PLL. This bidirectional pin must be placed on the PLL_FB_CLKOUTp pin for left / right PLLs, and on the PLL_FBp_CLKOUT1 pin for top / bottom PLLs.
The zero delay buffer clock output which is the compensated output clock of the PLL must be placed on the PLL_CLKOUTn pin for left / right PLLs, and on any of the remaining PLL_CLKOUT pins for top / bottom PLLs.
The bidirectional "mimic" I/O pin is always enabled, but Altera recommends it to remain unconnected on your board. If you do use it as a secondary clock, it will not have the same phase relationship with the zero delay buffer compensated clock output. Use timing simulation or timing analysis to determine the phase relationship to the compensated output clock. Also, any loading on the bidirectional mimic I/O pin will affect the timing on the zero delay buffer clock output. This will compromise the zero delay buffer feedback compensation mode and can lead to different phase shift results between the PLL source clock and the zero delay buffer compensated output clock.
More information on this feature is available in the respective device handbook.
Clock Networks and PLLs in Stratix III Devices (PDF)