Article ID: 000084305 Content Type: Troubleshooting Last Reviewed: 11/03/2014

Why are the values for FS (Full Swing) and LF (Low Frequency) zero when simulating a PCIe Hard IP core for Gen3?

Environment

  • Quartus® II Subscription Edition
  • Simulation
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    There is an issue with the PCIe® Hard IP simulation models when targeting the Stratix® V and Arria® V GZ device families, where the values for FS and LF are zero for Gen3.  Certain bus functional models (BFM) may report an error that FS and LF have values that violate the PCIe specification.

    Resolution This issue will be fixed in a future version of the Quartus® II software.  File a service request and reference the ID number FB156219 if updated simulation models are required. 

    Related Products

    This article applies to 4 products

    Arria® V GZ FPGA
    Stratix® V GS FPGA
    Stratix® V GT FPGA
    Stratix® V GX FPGA

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