Article ID: 000084365 Content Type: Troubleshooting Last Reviewed: 05/23/2023

Why does derive_pll_clocks fail to automatically constrain PLL output clocks?

Environment

  • Quartus® II Subscription Edition
  • PLL
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® II software, the Synopsys Design Constraint (SDC) command derive_pll_clocks may not properly constrain phase-locked loop (PLL) outputs. This problem occurs when your design uses PLL clock switchover in 28 nm devices, including Stratix® V, Arria® V, and Cyclone® V devices. Because of this problem, the derive_pll_clocks command does not automatically create the generated clocks on PLL outputs relative to each reference clock input.

    Resolution

    To work around this problem, constrain the PLL outputs manually using create_generated_clock SDC commands. Refer to the Related Articles section for more details.

    This problem is fixed starting with the Intel® Quartus® Prime Pro or Standard Edition Software version 11.0.

    Related Products

    This article applies to 14 products

    Cyclone® V SX SoC FPGA
    Cyclone® V GT FPGA
    Stratix® V GX FPGA
    Stratix® V GT FPGA
    Cyclone® V GX FPGA
    Stratix® V GS FPGA
    Arria® V GZ FPGA
    Arria® V SX SoC FPGA
    Cyclone® V ST SoC FPGA
    Arria® V ST SoC FPGA
    Arria® V GT FPGA
    Arria® V GX FPGA
    Stratix® V E FPGA
    Cyclone® V SE SoC FPGA