Description
The Quartus II software version 2.0 incorrectly gives this error when compiling APEX II designs and using the output clock from the phase-locked loop (PLL) to feed the
DDRIO
register clock ports in both positive and negative polarities. Although APEX II devices have a programmable clock inverter built into the I/O cell to accommodate this, the Quartus II software version 2.0 incorrectly prevents this action.
This problem is fixed in the Quartus II software version 2.0 SP1.