The local_burstbegin signal is missing in the full rate write avalon memory mapped waveforms in Figure 4-4 in DDR/DDR2 HP Controller user guide. Local_burstbegin follows the Avalon spec, where it is called beginbursttransfer. Table 3-1 in Avalon Interface Specifications (PDF) describes this signal as "Asserted by the system interconnect fabric for the first cycle of each transfer regardless of waitrequest and other signals."
In DDR2 HP Controller for writes, local_burstbegin should be asserted for one clock cycle at the beginning of each burst transfer. It should only stay high for one cycle per burst transfer, even if the slave has de-asserted local_ready (called waitrequest_n in Avalon). If the slave has de-asserted local_ready, the master must keep all the other request signals (local_write_req, local_addr, local_size etc) asserted until local_ready becomes high again, but local_burstbegin should not stay asserted.
local_burstbegin is also used for read trasactions where it is asserted for one clock cycle when the read request is asserted and the local_address from which the data should be read is given to the memory. If the local_ready(called waitrequest_n in Avalon) is deasserted, the master must keep all the request signals (local_read_req, local_address, local size etc) asserted until local_ready becomes high again, but local_burstbegin should not stay asserted.