Due to a problem in the Quartus® II software version 12.1, you may see this error in the Altera_PLL MegaWizard™ Plug-In Manager when using the Enable physical output clock parameters option manually set your M and N counter values even though the VCO frequency should be within the supported operating range of the device. This problem occurs when generating an Altera_PLL with an M counter value greater than 255 and an N counter value of 1.
If you require an M counter value of 256 or greater, and an N counter value of 1, you will need to perform the following steps in order to implement the desired setting for your Altera_PLL:
- Enter all of your desired parameters in the Altera_PLL megafunction with the following two exceptions:
- Enter a Reference Clock Frequency value equal to twice the value of your actual reference clock frequency.
- Enter a value of 2 for the Divide Factor (N-Counter).
(By using the N value of 2 and a reference clock frequency twice of your actual clock frequency, the MegaWizard Plug-In Manager will be able to generate legal settings for the Altera_PLL).
- Create the megafunction variation file by clicking Finish.
- Open the <pll_name>_0002.v file created by the Altera_PLL MegaWizard Plug-In Manager. This file is located in a sub-directory for your project in the <pll_name> folder. Make the required modifications to the following parameters:
- Locate the .reference_clock_frequency parameter. The value will be twice your desired clock frequency. Modify the value to equal the actual reference clock frequency.
- Locate the .n_cnt_bypass_en parameter and change the value from "false" to "true".
- Save and close <pll_name>_0002.v.
- If you are going to perform functional simulations of the Altera_PLL megafunction, make the same parameter changes from step 3 above in the <pll_name>.vo file, located in the <pll_name>_sim folder in your project directory.
This problem is scheduled to be fixed in a future version of the Quartus II software.