Article ID: 000084879 Content Type: Troubleshooting Last Reviewed: 06/07/2013

Does the Arria II GX PCIe example design take into account the pll_locked errata issue?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT

Critical Issue

Description

Yes, when using the altpcie_serdes_rs.v file for Arria® II GX device, the code is designed to hold off the tx_digitalreset assertion similar to the pll_locked_soft_logic available from the Arria II GX Errata. No additional user logic is needed to account for this issue.

For more information related to this erratum, refer to the "Transmitter PLL Lock (pll_locked) Status Signal" section of the Arria II GX Errata Sheet.

Arria II GX Errata Sheet (PDF)

 

Resolution

 

Related Products

This article applies to 1 products

Arria® II GX FPGA