Article ID: 000085043 Content Type: Product Information & Documentation Last Reviewed: 04/17/2023

How do I prevent PLL output counter merging in Quartus® II 12.1 and later for Intel® Stratix®, Arria® V and Cyclone® V FPGA devices?

Environment

  • Quartus® II Software
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    In Quartus® II versions 12.1 and later, you can use the QSF variable UNFORCE_MERGE_PLL_OUTPUT_COUNTER to prevent the PLL output counters from merging in Stratix® V, Arria® V, or Cyclone® V devices.

     

    Resolution

    Below is an example of the assignment being made to a PLL output counter:

    set_instance_assignment -name UNFORCE_MERGE_PLL_OUTPUT_COUNTER ON -to "mypll:inst|mypll_0002:mypll_inst|altera_pll:altera_pll_i*”

    Related Products

    This article applies to 15 products

    Cyclone® V SX SoC FPGA
    Stratix® V E FPGA
    Cyclone® V GT FPGA
    Stratix® V GX FPGA
    Stratix® V GT FPGA
    Cyclone® V GX FPGA
    Stratix® V GS FPGA
    Arria® V GZ FPGA
    Arria® V SX SoC FPGA
    Cyclone® V ST SoC FPGA
    Arria® V ST SoC FPGA
    Arria® V GX FPGA
    Arria® V GT FPGA
    Cyclone® V E FPGA
    Cyclone® V SE SoC FPGA