Article ID: 000085126 Content Type: Product Information & Documentation Last Reviewed: 08/13/2012

How is psuedo-differential I/O implemented in Stratix II device side I/O banks?



It is possible to create psuedo-differential I/O in Stratix® II device side banks by implementing two single-ended I/O pins.

Altera® recommends that you implement any psuedo-differential standards by using the existing differential pin pairs (i.e. LVDS & CLK). The reason for this is that these pin-pairs have a tighter skew margin than the non-differential normal I/O pins.

An output would simply be constructed by routing your signal to two output registers (one in each differential IOE Pin) one register clocked straight off your clock, the other off the inverse of your clock.

An input is basically the same, you need to use the differential pin pair but only the positive polarity input is used. In other words, only the non-inverted pin is required to be specified in the design, the inverted pin is reserved when a differential I/O standard is assigned. Any input will only use the positive signal, and is referenced to VREF (which is still required).


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Stratix® II FPGAs



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