Article ID: 000085362 Content Type: Product Information & Documentation Last Reviewed: 09/11/2012

How can I connect clock pins and PLL output clocks to the Global Clock Control Block in Stratix III and Stratix IV Devices?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The mapping between the input clock pins, PLL counter outputs, and clock control block inputs is as follows for Stratix® III and Stratix IV devices:

  • inclk[0] and inclk[1]—can be fed by any of the four dedicated clock pins on the same side of the device
  • inclk[2]—can be fed by PLL counters C0 and C2 from the two center PLLs on the same side of the device
  • inclk[3]—can be fed by PLL counters C1 and C3 from the two center PLLs on the same side of the device

For dynamic selection of these clock sources, you can use the ALTCLKCTRL megafunction in your design.

The corner PLLs (L1, L4, R1, and R4) and the corresponding clock input pins (PLL_L1_CLK and so forth) do not support dynamic selection for the GCLK network.

The clock source selection for the GCLK and RCLK networks from the corner PLLs (L1, L4, R1, and R4) and the corresponding clock input pins (PLL_L1_CLK and so forth) is controlled statically using configuration bit settings in the configuration file (.sof or .pof) generated by the Quartus® II software.

 

Related Products

This article applies to 4 products

Stratix® III FPGAs
Stratix® IV GT FPGA
Stratix® IV GX FPGA
Stratix® IV E FPGA