Article ID: 000085389 Content Type: Troubleshooting Last Reviewed: 09/11/2012

What is the status of the JTAG circuit during power-on-reset (POR)?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description The status of the JTAG circuit during POR is in Reset mode.

Related Products

This article applies to 1 products

Stratix® FPGAs