Article ID: 000086062 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why does the runtb_vcs.do script fail for PCIe root port example testbench?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem in the Quartus® II software version 13.0 and later, a Qsys system that contains an AXI Default Slave but no AXI Slave will not compile and simulate correctly. The following error will be reported during simulation: 

Modelsim :  ** Error <system_name>_mm_interconnect_0_addr_router.sv(196): (vlog-2730) Undefined variable: 'write_transaction'

Synopsys VCS : Error-[IND] Identifier not declared <system_name>_interconnect_0_addr_router.sv, 196
  Identifier 'write_transaction' has not been declared yet. If this error is not expected, please check if you have set include "altpcietb_bfm_vc_intf_ast_common.v" 
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To workaround the issue, you need to implement the following steps:

1.  Remove the following redundant files in sim_filelist that are also defined in the altpcietb_bfm_ep_example_chaining_pipen1b.vo:

altpcierd_cdma_ecrc_check_128.v
altpcierd_cdma_ecrc_check_64.v
altpcierd_cdma_ecrc_gen.v
altpcierd_cdma_ecrc_gen_calc.v
altpcierd_cdma_ecrc_gen_ctl_128.v
altpcierd_cdma_ecrc_gen_ctl_64.v
altpcierd_cdma_ecrc_gen_datapath.v
altpcierd_rx_ecrc_128.vo
altpcierd_rx_ecrc_64.vo
altpcierd_tl_cfg_sample.v
altpcierd_tx_ecrc_128.vo
altpcierd_tx_ecrc_64.vo
altpcierd_tx_ecrc_ctl_fifo.v
altpcierd_tx_ecrc_data_fifo.v
altpcierd_tx_ecrc_fifo.v
altpcierd_pcie_reconfig.v

2. Open altpcietb_bfm_ep_example_chaining_pipen1b.vo" under  <project_dir>/<variation>_examples/common/testbench directory

3. Rename the declaration of the second module by appending “_altcrc” to the original name on the lines listed below
-  Line 23425 change altpcierd_rx_ecrc_128 to altpcierd_rx_ecrc_128_altcrc
-  Line 29557 change altpcierd_rx_ecrc_64  to altpcierd_rx_ecrc_64_altcrc 
-  Line 33081 change altpcierd_tx_ecrc_128 to altpcierd_tx_ecrc_128_altcrc
-  Line 39787 change altpcierd_tx_ecrc_64  to altpcierd_tx_ecrc_64_altcrc 

4. Modify the runtb_vcs.sh for the following
- Change QUARTUS_ROOTDIR to point to your current Quartus installation directory
- Add “–cla” option to the command line after “vcs”
- Add “ ../” after “ incdir” to include directory above testbench for the script to find altpcietb_bfm_vc_intf_ast_common.v

The new command will look like the following:
vcs -lca -ntb_opts check -R vcs lic wait error 100 v2k incdir ../ ../../common/testbench/ ../../common/incremental_compile_module -f sim_filelist.f -l transcript

This problem will be fixed in future Quartus II software versions.

Related Products

This article applies to 1 products

Cyclone® IV GX FPGA