Article ID: 000086282 Content Type: Troubleshooting Last Reviewed: 05/31/2017

Why do I see data coherency failures on my SOC design?

Environment

  • Intel® Quartus® Prime Pro Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the default configuration of the CoreLink™ Level 2 Cache Controller L2C-310 in linux-socfpga kernel prior to 4.10, data coherency failures may be seen.

    For Linux-socfpga kernels prior to 4.10, the L2C-310 cache controller has the Shared attribute override enable bit is set to OFF.

    This allows the controller to optimiase some non-cacheable accesses from the MPU cores or ACP port into Cacheable non-allocated accesses, and moves the point of coherency from the SDRAM to the L2 Cache.    

    The change in the point of coherency could cause problems if masters access the SDRAM via L3 or the FPGA2SDRAM bridge.

    Reference: CoreLink™ Level 2 Cache Controller L2C-310, Revision: r3p3 Technical Reference Manual (ARM DDI 0246H (ID080112)): Section 2.3.2 Shareable attribute.   

     

    Resolution

    It is recommended that the Aux Control register bit [22]: Shared attribute override enable bit is set to ON.    This setting disables optimizations in the L2 Cache controller.

    This problem is fixed in the latest linux-socfpga and u-boot-socfpga versions available from https://github.com/altera-opensource/

    Related Products

    This article applies to 6 products

    Cyclone® V ST SoC FPGA
    Cyclone® V SE SoC FPGA
    Arria® V SX SoC FPGA
    Arria® V ST SoC FPGA
    Intel® Arria® 10 FPGAs and SoC FPGAs
    Intel® Arria® 10 SX SoC FPGA

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