The SmartVID feature is implemented via a soft IP in the Arria® 10 FPGA core. As such, the FPGA logic needs to be configured successfully before SmartVID is functional. If you use the Early I/O Configuration method to boot the Arria 10 HPS first prior to configuring the FPGA, the SmartVID feature will not be available until FPGA core configuration is complete.
Ensure that both VCC and VCCP of the device is powered with a fixed nominal voltage (0.90V) during Early I/O configuration. Once FPGA configuration is complete, the SmartVID IP will be able to request the power regulator to update the value of VCC and VCCP.
This information will be included in a future release of the Arria 10 Handbook.