If you have designed your system:
1. Based on Quartus® II software version 9.0 DDR2 SDRAM full-rate column I/Os specifications for Cyclone® III device and
2. After migrating to Quartus II software 9.1, and changing the design to use DDR2 SDRAM High Performance controller II
You might observe core timing failures and performance degradation.
In order to achieve higher clock rate and remove core timing violations consider the guidelines below:
I. Make sure you are using AFI-based PHY.
II. In Quartus II software, click on Assignments pull down and select Settings
1. Click on Physical Synthesis Optimizations.
a. Set the effort level to Extra.
b. In Optimize for performance section, enable all the options.
2. Click on Analysis & Synthesis Settings and set Optimization technique to Speed.
III. If you need to perform board re-layout, make sure all the interface pins are placed on one side (top or bottom).