Article ID: 000086557 Content Type: Troubleshooting Last Reviewed: 10/05/2015

Why is the top view of MAX10 for V36 and V81 packages in Pin Planner different than the package outline drawing?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® II software version 15.0 Update 1 and earlier, the top view and bottom view of MAX®10 devices in V36 and V81 packages shown in Pin Planner are swapped.

    There is no impact to the pin-out of the devices. The V36 and V81 package drawings as well as Cadence symbols are correct.

    Resolution

    The pin locations in top and bottom view have been corrected in the Quartus II software version 15.0 update 2.

    The positions of the I/O bank label and red dot indicator are scheduled to be fixed in a future version of the Quartus II software.

    Related Products

    This article applies to 1 products

    Intel® MAX® 10 FPGAs