Article ID: 000086807 Content Type: Troubleshooting Last Reviewed: 03/21/2022

xmelab: *F,CUMSTS: Timescale directive missing on one or more modules.

Environment

  • Intel® Quartus® Prime Pro Edition
  • External Memory Interfaces Intel® Stratix® 10 FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.1, you may see this error message while simulating the High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example with the Cadence* Xcelium* simulator.

    Resolution

    To work around this problem in the Intel® Quartus® Prime Pro Edition Software version 21.1, follow the steps below:

    1. Go to <example_design_path>/sim/ed_sim/sim/xcelium/
    2. Open xcelium_setup.sh with your preferred text editor
    3. Locate 'USER_DEFINED_ELAB_OPTIONS' line and add the '-timescale  1ps/1ps' option. After editing xcelium_setup.sh, the 'USER_DEFINED_ELAB_OPTIONS' line will look as follows:  USER_DEFINED_ELAB_OPTIONS="-timescale  1ps/1ps"
    4. Execute ./xcelium_setup.sh

    This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.3.

     

     

     

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 MX FPGA