When using an Intel® Arria® 10 FPGA quarter-rate DDR4 controller in the Quartus® II software version 14.1, you might find the CAS_n-to-CAS_n command delay to different bank groups does not meet the tCCD_S parameter setting in the Intel Arria 10 DDR4 Controller Intel® FPGA IP GUI. For example, you may set tCCD_S as 4 in the GUI, but the simulation waveform shows an 8. This results in gaps between consecutive read or write transactions.
As a workaround, you can change the following parameters:
From:
.SEC_HMC_CFG_RD_TO_RD_DIFF_BG (2),
.PRI_HMC_CFG_RD_TO_RD_DIFF_BG (2),
.SEC_HMC_CFG_WR_TO_WR_DIFF_BG (2),
.PRI_HMC_CFG_WR_TO_WR_DIFF_BG (2),
To:
.SEC_HMC_CFG_RD_TO_RD_DIFF_BG (1),
.PRI_HMC_CFG_RD_TO_RD_DIFF_BG (1),
.SEC_HMC_CFG_WR_TO_WR_DIFF_BG (1),
.PRI_HMC_CFG_WR_TO_WR_DIFF_BG (1),
These parameters exist in the following files for synthesis or simulation purposes:
- <working_dir>/emif_<instance_num>_example_design/sim/altera_emif_<acds version>/sim/ ed_sim_altera_emif_<acds version>_*.v
- <working_dir>/emif_<instance_num>_example_design/qii/altera_emif_<acds version>/synth/ ed_synth_altera_emif_<acds version>_*.v
- <working_dir>/<core_name>/altera_emif_<acds version>/synth/<core_name>_altera_emif_<acds version>_*.v
- <working_dir>/<core_name>/altera_emif_<acds version>/sim/<core_name>_altera_emif_<acds version>_*.v
This problem is scheduled to be fixed in a future release of the Quartus II software.