The ALTGX Megawizard™ allows maximum of 10 input reference clocks as sources to the ATX_PLL. When the user selects values from 1 through to 9 for the ATX PLL in the ‘What is the selected input clock source for the Rx/Tx PLLs?’ option the design fails compilation. Quartus® II software will produce an error saying for example that inclk  of ATX PLL cannot be connected.
The following workaround is required
- Select ‘0’ as the input clock source for the ATX PLL and
- Connect the pll_inclk_rx_cruclk  as the input clock source for the ATX PLL in your design
This problem occurs in Quartus II software version 9.1 and is scheduled to be fixed Quartus II software version 9.1 SP1.