Description
Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 20.1, you may see this Internal Error when you connect the "pll_ref_clk" port of External Memory Interfaces Intel® Stratix® 10 FPGA IP to an unsupport clock source such as Clock Source BFM Intel® FPGA IP.
Resolution
To avoid this error, drive the "pll_ref_clk" from the external clock pin directly.