The HDMI Intel® FPGA IP may momentarily lose video lock when used on Intel® Stratix® 10 L or H-Tile transceiver devices in the Intel® Quartus® Prime Pro Edition Software v21.3 and earlier if your source transmits a high frequency clock pattern when it is not transmitting valid video.
The HDMI Intel FPGA IP for Intel Stratix 10 L or H-Tile transceiver devices perform word alignment in the core fabric HDMI Intel FPGA IP. The Intel Stratix 10 L or H-Tile Transceiver Native PHY IP Word Aligner is not intended to be used for Intel Stratix 10 L or H-Tile devices and is configured with a word alignment pattern of 0xAAAAA which normally should not be present in a video stream. However, some 3rd party video sources may transmit a clock pattern when not sending valid video traffic.
The combined action of the Intel Stratix 10 L or H-Tile Transceiver Native PHY IP Word Aligner and core fabric HDMI Intel FPGA IP Word Aligner may cause a momentary acquisition, loss, and re-acquisition of video lock in the HDMI Intel FPGA IP when the received signal transitions from a clock pattern to valid video.
To work around this problem, configure the Intel Stratix 10 L or H-Tile Transceiver Native PHY IP Word Aligner in Bitslip mode and connect the rx_bitslip port to ‘0’ to prevent it from making a false word alignment. You will need to edit the clear text code to add the rx_bitslip port and connect it to ‘0’.
This problem is scheduled to be fixed in a future version of the Intel® Quartus® Prime Pro Edition Software.
