Due to a problem in the Intel® Quartus® Prime Pro edition Software version 21.4, you may see this error during the Tile Logic Generation (TLG) stage of a Partial Reconfiguration (PR) compile. This problem occurs in PR designs that implement F-Tile dynamic reconfiguration and only affects Intel Agilex® designs.
To work around this problem, skip the TLG stage in the compile and proceed directly to Analysis & Synthesis for the PR implementation flow.
This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.