Article ID: 000091595 Content Type: Error Messages Last Reviewed: 05/09/2023

Why does the F-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example simulation fail with signal rx_gb_underflow_err being asserted?

Environment

  • Intel® Quartus® Prime Pro Edition
  • ModelSim*-Intel® FPGA Edition Software
  • Questa*-Intel® FPGA Edition
  • JESD204B Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the ModelSim*-Intel® FPGA Edition 2021.4 and Questa* Intel® FPGA Edition 2022.1, a variation in rx_phy_clk frequency leads to the signal rx_gb_underflow_err being asserted.
    This problem is observed only in the following variant:
    L = 16, M = 8, F = 2, DATA RATE/L = 32000.000000Mbps, FCLK_MULP = 1, WIDTH_MULP = 4

     

     

     

    Resolution

    This problem impacts Intel® Quartus® Prime Software IP versions 22.2 and 22.3.

    To work around this problem:

    For ModelSim*, run the simulation using v2022.1 instead of v2021.4.
    For Questa*, run the simulation using v2021.3 instead of v2022.1.

    This problem has been fixed in the ModelSim* Intel® FPGA Edition and Questa* Intel® FPGA Edition 22.4. 

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs