Article ID: 000092438 Content Type: Error Messages Last Reviewed: 10/07/2022

Error(272006): MGL_INTERNAL_ERROR: Port <altera_syncram_instance_hierarchy> inst altera_syncram_impl1|dffe inst ecc_addr_reg|d has already been assigned

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2 and earlier, you might see this error message during compilation in the synthesis stage for Simple Dual Port RAM when using the following configurations:

    · Parameter device_family = "Agilex"

    · Parameter ram_block_type = "M20K"

    · Parameter enable_ecc = "TRUE"

    · Parameter address_aclr_b = "ACLEAR"

    · Parameter outdata_reg_b = "CLOCK0/CLOCK1"

    · Width x numwords is more than 20480 bits (more than 1 M20K used)

    · No read enable signal is used

     

     

    Resolution

    A patch is available to fix this problem for the Intel® Quartus® Prime Pro Edition software version 21.4 and 22.2  

    Download and install the patches from the following links:

    For Intel® Quartus® Prime Pro Edition Software version 21.4:

    For Intel® Quartus® Prime Pro Edition Software version 22.2:

    This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 22.3.

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs