Intel® FPGA Design Examples
Intel® design examples provide efficient solutions for common design challenges. These designs can be used as a starting point for developing with your unique system and are available using many functions such as filters, arithmetic functions, error detection/correction, modulation/demodulation, and video and image processing.
Design examples are also available in the Design Store for Intel® FPGAs and RocketBoards.org.
OpenCL Mandelbrot Fractal Algorithm example provides a kernel that implements the Mandelbrot fractal algorithm as well as a host application that displays the results to the screen.
The objective of this example is to showcase the way to constraint the TSE_RGMII. It can run on 3 different speeds which are 10 MHz, 100 MHz, and 1000 MHz.
Discover download files, system requirements and features for the Serial RapidIO to TI 6482 DSP reference design in this guide from the Intel support team.
PCI Express* (PCIe*) protocol is a high-performance, scalable, and feature-rich serial protocol with data transfer rates from 2.5 gigatransfers per second (GT/s) to 16.0 GT/s.
The Intel drive-on-a-chip motor control reference design is an integrated drive system on a single Cyclone V SoC or Intel MAX 10. Learn more in this guide.
Intel® FPGA SDK for OpenCL™ Design Examples
Search Intel's content collection of development guides, training, software downloads and software kits for FPGA SDK for OpenCL.
This example describes a 64 bit x 8 bit synchronous, true dual-port RAM design with any combination of independent read or write operations in the same clock cycle in VHDL.
This example describes a 64-bit x 8-bit dual clock synchronous RAM design with different read and write addresses in VHDL. Learn more about the synchronous design from Intel.
This VHDL 1x64 shift register design example describes a single-bit wide, 64-bit long shift register in VHDL. Learn more about this design from Intel.
This example describes a 64-bit x 8-bit single-port RAM design with common read and write addresses in VHDL. Learn more about this design from Intel.
This example describes a 16-bit binary adder tree in VHDL. Devices with 4-input lookup tables in logic elements (LEs) can improve performance with a binary adder tree structure.