The Designing Digital Down Conversion Systems design example, featuring cascaded-integrator-comb (CIC) and finite impulse response (FIR) Compiler functions, demonstrates a multichannel, multirate digital system using digital signal processing (DSP) intellectual property (IP).
Sample rate conversion has a wide range of applications in modern digital systems, especially wireless communications systems such as WCDMA and WiMAX systems. Efficient implementation of decimation and interpolation can be accomplished by concatenating CIC and FIR filters.
This example demonstrates a data rate down conversion system that can be commonly seen in time division multiplexing (TDM) WiMAX receivers. The overall system diagram is shown in Figure 1.
The input to the design example is from two independent data sources, such as the in-phase (I) and quadrature (Q) components of a digital communications system. The in-phase signal is a sine wave with a center frequency of 4.57 MHz. The quadrature signal is a cosine wave also centered at 4.57 MHz. The combined, time multiplexed input data stream is sampled at 182.784 MHz, so the corresponding data rate for the in-phase and quadrature signals is 91.392 MHz. Part of the input signal is corrupted by high-frequency additive noise.
The CIC and FIR filters convert in-phase and quadrature signals sample rate to 11.484 MHz while maintaining the input signals spectrum information. The decimation filters also reject out-of-band noise. Therefore, the output of this rate conversion system should be noiseless down sampled sinusoidal waves of frequency 4.57 MHz. For well defined rate change systems, the narrow band information signal should maintain its spectrum from input to output, as demonstrated in this design example.
- Decimation or interpolation is implemented efficiently using the CIC Compiler IP.
- FIR Compiler is configured to have an inverse sinc frequency response to compensate CIC filter droop.
- A MATLAB* script designing CIC compensating filter is provided for your reference. The script uses the frequency sampling method to design a FIR filter that has an inverse sinc frequency response. The overall system response is plotted for you to verify key system specifications such as the pass-band ripple and stop-band attenuation.
- Multiple input data sources are supported. For wireless and wireline applications, input data can be viewed as time division multiplexed. For other applications, data sources can be viewed as interleaved.
- Packet Format Converter is included to properly de-interleave multiple data sources for display.
- Avalon® Streaming (Avalon-ST) Interface transfers packet data from multiple data sources between cores. For more information about Avalon-ST, please refer to the Avalon® Interface Specifications (PDF).
Download the files used in this example:
- Download DDC Example Design File (Version 71)
- Download DDC Example README File (Version 71)
- Download DDC Example Design File (Version 61)
- Download DDC Example README File (Version 61)
The use of this design is governed by, and subject to, the terms and conditions of the Hardware Reference Design License Agreement.
Files in the zip download include:
- TDMDDC.mdl - DSP Builder design file
- ciccomp.m - MATLAB script for designing an inverse sinc CIC compensation filter
- cic.vhd - wrapper file to generate the CIC Compiler IP core
- fir.vhd - wrapper file to generate the FIR Compiler IP core
- fdcoeffR4N8M1L110.txt - pre-generated compensating FIR filter coefficients
CIC and Compensation FIR Design Example in DSP Builder for Intel® FPGAs
Table 1 shows the overall frequency response specifications. Select parameters for CIC and FIR filters (see Tables 2 and 3) based on the frequency response requirement.
Table 2. Parameters for CIC Filter
|Number of Stages||8|
|Rate Change Factor||4|
|Number of Interfaces||1|
|Number of Channels Per Interface||2|
|Input Data Width||8|
|Output Data Width||16|
Table 3. Parameters for FIR Filter
|Rate Specification||Decimation by 2|
|Input Bitwidth||Signed binary 16|
|Output Bitwidth||Full resolution|
|Device Family||Stratix® II|
|Clocks per Output Data||2|
|Coefficients Input||From file|