VHDL: Signed Multiplier-Accumulator



This example describes an 8-bit signed multiplier-accumulator design with registered I/O ports and a synchronous load input in VHDL. Synthesis tools are able to detect multiplier-accumulator designs in the HDL code and automatically infer the altmult_accum megafunction or map the logic to DSP blocks in the target device architecture.

Figure 1. Signed multiply-accumulator top-level diagram.

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