Timing exceptions modify the default analysis that is performed by the Timing Analyzer. This section describes the following available timing exceptions:
If a conflict of node names occurs between timing exceptions, the following order of precedence applies:
- False path
- Minimum delays and maximum delays
- Multicycle path
The false path timing exception has the highest precedence. Within each category, assignments to individual nodes have precedence over assignments to clocks. Finally, the remaining precedence for additional conflicts is order-dependent, such that the last assignments overwrite (or partially overwrite) earlier assignments.